When fabricating integrated circuits (IC), layers of insulating, conducting and semiconducting materials are deposited and patterned. Contact vias or openings are commonly formed in insulating materials known as interlevel dielectrics (ILDs). The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring at various levels. Damascene processing similarly involves etching trenches in insulating layers in a desired pattern for a wiring layer. These trenches are then filled with conductive material to produce the integrated wires. Where contact vias, extending downwardly from the bottom of the trenches, are simultaneously filled, the process is known as dual damascene.
Conductive elements, such as gates, capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper IC operation. In addition to interlevel dielectrics surrounding contacts, care must be taken to avoid conductive diffusion and spiking, which can cause undesired shorts between devices and contacts. Protective barriers are often formed between via or trench walls and metals in a substrate assembly, to aid in confining deposited material within the via or trench walls. Barriers are thus useful for damascene and dual damascene interconnect applications, particularly for small, fast-diffasing elements such as copper. Barriers also have application over transistor active areas and other circuit elements from or to which dopants tend to migrate during high temperature processing.
Candidate materials for protective barriers should foremost exhibit effective diffusion barrier properties. Additionally, the materials should demonstrate good adhesion with adjacent materials (e.g., oxide via walls, metal fillers). For many applications, a barrier layer is positioned in a current flow path and so must be conductive. Typically, barriers have been formed of metal nitrides (MNx) such as titanium nitride (TiN) or tungsten nitride (WN), which are dense, amorphous and adequately conductive for lining contact vias and other conductive barrier applications.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), forcefill, hot metal reflow, etc. These methods attempt to completely fill deep, narrow openings without forming voids or keyholes. More recently, processing advancements have enabled the employment of copper as an interconnect material, taking advantage of its low resistivity. Typically, copper is electroplated over the substrate surface in order assure adequate filling of deep vias or trenches.
It is difficult, however, to satisfactorily electroplate copper (Cu) directly over the metal nitride barriers. Although metal nitrides can be sufficiently conductive for circuit operation, where current flows through the thickness of the barrier layer, lateral conductivity across such layers is inconsistent. High sheet resistivity makes it difficult to maintain an equipotential surface. Accordingly, a seed layer of copper is typically first deposited over the barrier, such as by PVD, and the workpiece is then transferred to an electroplating bath to complete the deposition. The seed layer thus represents an additional processing step, adding significantly to process overhead.
Accordingly, there is a need for improved processes and materials for protective barriers in integrated circuits. Desirably, such processes should also be compatible with conventional fabrication techniques, and thereby easily integrated with existing technology.